解题思路：

       题目要求编写一个序列发生器，序列的内容是固定的，而且没有输入信号。即每个状态的输出只与当前状态有关，和输入无关，是摩尔型有限状态机的特征。使用摩尔状态机可以实现功能。

解题过程：

       功能较简单，使用一段式状态机即可。

       定义状态机变量，每个输出之后跳变到下一个状态。

 parameter     idle = 3'd0,

                            s1_0 = 3'd1,

                            s2_00 = 3'd2,

                            s3_001 = 3'd3,

                            s4_0010 = 3'd4,

                            s5_00101 = 3'd5,

                            s6_001011 = 3'd6;

       reg state;

       always @(posedge clk or negedge rst_n)

              if(!rst_n)

                     state <= 0;

              else case (state)

                     3'd0:     

                            begin

                                   state <= s1_0;

                                   data <= 0;

                            end

                     3'd1:     

                            begin

                                   state <= s2_00;

                                   data <= 0;

                            end

                     3'd2:     

                            begin

                                   state <= s3_001;

                                   data <= 1;

                            end

                     3'd3:     

                            begin

                                   state <= s4_0010;

                                   data <= 0;

                            end

                     3'd4:     

                            begin

                                   state <= s5_00101;

                                   data <= 1;

                            end

                     3'd5:     

                            begin

                                   state <= s6_001011;

                                   data <= 1;

                            end

                     3'd6:     

                            begin

                                   state <= s1_0;

                                   data <= 0;

                            end                     

                     default :

                            begin

                                   state <= idle;

                                   data <= 0;

                            end

                     endcase

       注意定义default所对应的动作。防止可能综合出锁存器。

仿真结果： 
`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
	parameter 	idle = 3'd0,
				s1_0 = 3'd1,
				s2_00 = 3'd2,
				s3_001 = 3'd3,
				s4_0010 = 3'd4,
				s5_00101 = 3'd5,
				s6_001011 = 3'd6;

	reg [2:0]state;
	always @(posedge clk or negedge rst_n)
		if(!rst_n) begin
			state <= 0;
			data <= 0;
			end
		else case (state)
			3'd0:	
				begin
					state <= s1_0;
					data <= 0;
				end
			3'd1:	
				begin
					state <= s2_00;
					data <= 0;
				end
			3'd2:	
				begin
					state <= s3_001;
					data <= 1;
				end
			3'd3:	
				begin
					state <= s4_0010;
					data <= 0;
				end
			3'd4:	
				begin
					state <= s5_00101;
					data <= 1;
				end
			3'd5:	
				begin
					state <= s6_001011;
					data <= 1;
				end
			3'd6:	
				begin
					state <= s1_0;
					data <= 0;
				end				
			default :
				begin
					state <= idle;
					data <= 0;
				end	
			endcase

				
endmodule



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