题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    reg [3:0] count;
    //计数 赋值
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            count<='d0;
        else if(set)                           //这句为置数功能的体现，计数位在满足条件时可以灵活改变计数结果
            count<=set_num;
        else
            count<=count+1;
    end
    //zero
    always@(posedge clk or negedge rst_n) begin //我想出题人可能没有考虑到number本身可以充当计数功能，所以额外给出了一个计数寄存器
        if(!rst_n)                                  
            zero=0;
        else if(count=='d0)
            zero<=1;
        else
            zero<=0;
    end
    //置位
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            number<='d0;
        else
            number<=count;
    end
 
endmodule