/*led每1秒翻转一次,周期为2s,系统时钟频率是50M,(1/50M)20ns为一个周期*/

/*方法一:通过分频来实现*/
`timescale 1ns / 1ps
module LED_1(
input clk,
input Rst_n,
output reg led
);
reg [31:0]div_cnt;
reg divclk;
always@(posedge clk or negedge Rst_n)
begin
	if(!Rst_n)
	begin div_cnt=0;led<=0;divclk<=0;end
	else if(div_cnt==50000000)//2s/20ns÷2,将ns换算成s后计算
	begin divclk<=~divclk;div_cnt<=0;end
	else div_cnt<=div_cnt+1'b1;
end
always@(posedge divclk)
	begin
	led=~led;
	end
	
endmodule




/*方法二:通过计数来实现   */
`timescale 1ns / 1ps
module LED_1(
input clk,
input Rst_n,
output reg led
);
reg [31:0]div_cnt;
//reg divclk;
always@(posedge clk or negedge Rst_n)
begin
	if(!Rst_n)
	begin div_cnt=0;led<=0;end
	else if(div_cnt==50000000)//2s/20ns÷2,将ns换算成s后计算
	begin div_cnt<=0;led=~led;end
	else div_cnt<=div_cnt+1'b1;
end
	
endmodule



/*Testbench*/
module LED_1_tst();
reg clk;
reg Rst_n;
wire led;

LED_1 uut(.clk(clk),
.Rst_n(Rst_n),
.led(led));
initial
	begin
		clk=0;
		Rst_n=0;
		#100 Rst_n=1;
		//#1000 $finish;
	end
always #10 clk=~clk;
endmodule

具体分频怎么计算的,可以参考我的上一篇博客Verilog中分频数的计算