手撕代码：1011001序列检测（2bit输入）乐鑫科技笔试题

1、题目
模块持续每拍并行输入2bit数，请实现对(1011001)2的序列检测功能，输入数据的顺序为高位2bit先输入，当检测到该序列时，输出一拍高电平脉冲信号。请用Verilog完整描述该模块。
2、状态机
我设计的是一个mealy状态机

3、veriloig代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/06/10 09:21:26
// Design Name: 
// Module Name: sequence_check_2bit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module sequence_check_2bit(
input clk,
input rst_n,
input [1:0]data_in,
input din_en,
output reg valid_flg
    );
	
reg [1:0]state;
parameter s0_idle=2'b00,
          s1=2'b01,//10
		  s2=2'b10,//1011
		  s3=2'b11;//101100

always @(posedge clk or negedge rst_n)
if(!rst_n)
	begin
		state<=s0_idle;
		valid_flg<=0;
	end
else
		begin
			case(state)
				s0_idle:
					if(din_en==1&&data_in==2'b10)
						begin state<=s1;valid_flg<=0;end
					else begin state<=s0_idle;valid_flg<=0;end
				s1:
				//10
				if(din_en)
					begin
						case(data_in)
						2'b00: begin state<=s0_idle;   end
						2'b01: begin state<=s0_idle;   end
						2'b10: begin state<=s1;        end
						2'b11: begin  state<=s2;       end
						endcase
					end
				else begin state<=s1;valid_flg<=0;end
				s2:
				//1011
				if(din_en)
					begin
						case(data_in)
						2'b00:begin state<=s3;  end
						2'b01:begin state<=s0_idle;  end
						2'b10:begin state<=s1;  end
						2'b11:begin state<=s0_idle;  end
						endcase
					end
				else begin state<=s2;valid_flg<=0;end
				s3:
				//101100
				if(din_en)
					begin
						case(data_in)
						2'b00:begin state<=s0_idle;valid_flg<=0;   end
						2'b01:begin state<=s0_idle;valid_flg<=0;   end
						2'b10:begin state<=s1;     valid_flg<=1;   end
						2'b11:begin state<=s0_idle;valid_flg<=1;   end
					    endcase
					end
				else begin state<=s3;valid_flg<=0;end
				default:begin  state<=s0_idle;valid_flg<=0;end
				endcase
		
		end
	
endmodule

testebench

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/06/10 09:57:36
// Design Name: 
// Module Name: sequence_check_2bit_tst
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module sequence_check_2bit_tst();

reg      clk;
reg      rst_n;
reg [1:0]data_in;
reg      din_en;
wire     valid_flg;

sequence_check_2bit u_sequence_check_2bit(
.clk      (clk      ),
.rst_n    (rst_n    ),
.data_in  (data_in  ),
.din_en   (din_en   ),
.valid_flg(valid_flg)
);
initial
	begin
		clk=1;
		rst_n=0;
		data_in=2'b00;
		din_en=0;

		#20 rst_n=1;
		    din_en=1;
		#20 data_in=2'b00;
		#20 data_in=2'b10;
		#20 data_in=2'b10;
		#20 data_in=2'b11;
		#20 data_in=2'b00;
		#20 data_in=2'b00;
		#20 data_in=2'b10;
		#20 data_in=2'b11;
		#20 data_in=2'b00;
		#20 data_in=2'b11;
		#20 data_in=2'b10;
		#20 data_in=2'b11;
		#20 data_in=2'b00;
		#20 data_in=2'b10;		
	    #20 din_en=0;
		   rst_n=0;
	
	end
always #10 clk=~clk;
	

	
endmodule