目录

代码

题目比较简单,直接上代码:

`timescale 1ns/1ns
module data_minus(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output  reg [8:0]c
);
    always @(posedge clk or negedge rst_n) begin
        if (~rst_n) begin
            c <= 9'b0;
        end
        else 
            c <= a>b? (a-b): (b-a);
    end
endmodule

简析