题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match );

reg[7:0] n_state,c_state;

always @ (posedge clk or negedge rst_n)
    if (!rst_n)
         c_state <= 0;
    else 
         c_state <= n_state;





reg flag;

always @ (posedge clk or negedge rst_n)
    if(!rst_n)
    begin
        flag <= 0;
        n_state <= 0;
        end
    else 
        begin
            case(n_state)
                8'd0:     
                    if (a==0)
                        n_state <= 8'd1;
                    else
                        n_state <= 0;
                8'd1:     //0
                    if(a==1)
                        n_state <= 8'd2;
                    else
                        n_state <=  8'd1;
                8'd2:     //01
                    if(a==1)
                        n_state <= 8'd3;
                    else
                        n_state <= 8'd2;
                
                8'd3:     //011
                    if(a==1)
                        n_state <= 8'd4;
                    else
                        n_state <= 8'd3;
                
                
                
                8'd4:     //0111
                    if(a==0)
                        n_state <= 8'd5;
                    else
                        n_state <=8'd4;
                8'd5:     //0111 0
                    if(a==0)
                        n_state <= 8'd6;
                    else
                        n_state <= 8'd2;
                8'd6:     //0111 00
                    if(a==0)
                        n_state <= 8'd7;
                    else
                        n_state <= 8'd2;
                8'd7:     //0111 000
                    if(a==1)
                    begin
                        flag <= 1;
                        n_state <= 8'd8;
                     end
                    else
                        n_state <= 8'd2;
                 8'd8:     //0111 0001
                 begin
                        n_state <= 8'd0;
                        flag <= 0;
                        end
                default:  n_state <= 8'd0; 
            endcase
            
        end

    always @ (posedge clk or negedge rst_n)
    if (!rst_n)
         match <= 0;
     else if(flag)
          match <= 1;
     else
           match <= 0;

endmodule

经典三段式状态机，开始的时候进入误区，序列出现错误就回到初始状态就返回0，这样是错的，后四位一旦出错，也就是01，则应该回到第二个状态，前四位出错没辙； 还有一个错误，第二段状态机的flag信号因为第二段always是时钟检测，导致flag会落后一个时钟导致错误；如果采用always@（）会出现啥情况我去试试；（好了，试了回来，因为tb给的信号是按时钟给的，会出错） 最后一段还不能用always@（） 这样会领先答案一个时钟，我也是醉了。 正确的 错误的 ![alt] (https://uploadfiles.nowcoder.com/images/20220406/902437400_1649250677697/086D7D2BBFB9CD57CEB0792016F74CB1)