目录

代码

题目简单，直接上代码：

`timescale 1ns/1ns
module data_select(
    input clk,
    input rst_n,
    input signed[7:0]a,
    input signed[7:0]b,
    input [1:0]select,
    output reg signed [8:0]c
);
    always@(posedge clk or negedge rst_n) begin
        if (~rst_n) begin
            c <= 9'b0;
        end
        else
            case (select)
                2'b00: c <= a;
                2'b01: c <= b;
                2'b10: c <= a + b;
                2'b11: c <= a - b;
                default: c <= 9'b0;
            endcase
    end
endmodule

简析

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