题解 | #含有无关项的序列检测#

思路同输入序列连续的序列检测，既可以用移位寄存器，又可以用状态机。

代码

移位寄存器

module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    reg [8:0] a_r;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            match <= 1'b0;
        else 
            match <= (a_r[2:0] == 3'b110) && (a_r[8:6] == 3'b011);
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            a_r <= 9'b0;
        else
            a_r <= {a_r[7:0], a};
    end
endmodule

状态机

下面的状态机不够完善，没法检测重复序列，目前也没有简单点的解决方法。

module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
);
    parameter ZERO=0, ONE=1, TWO=2, THREE=3, FOUR=4, FIVE=5, SIX=6, SEVEN=7, EIGHT=8, NINE=9;
    reg [3:0] state, nstate;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            state <= ZERO;
        else
            state <= nstate;
    end
    
    always@(*) begin
        case(state)
            ZERO   : nstate = a? ZERO : ONE;
            ONE    : nstate = a? TWO  : ONE;
            TWO    : nstate = a? THREE: ONE;
            THREE  : nstate = FOUR;
            FOUR   : nstate = FIVE;
            FIVE   : nstate = SIX;
            SIX    : nstate = a? SEVEN: ONE;
            SEVEN  : nstate = a? EIGHT: ONE;
            EIGHT  : nstate = a? ZERO: NINE;
            NINE   : nstate = a? TWO  : ONE;
            default: nstate = ZERO;
        endcase
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            match = 0;
        else
            match = state==NINE;
    end
  
endmodule