简析
题目要求使用D触发器对时钟进行二分频、四分频和八分频。
D触发器
真值表:
clk | D | Q | Q* |
---|---|---|---|
0 | 0 | 0 | |
0 | 1 | 0 | |
1 | 0 | 1 | |
1 | 1 | 1 |
D是触发器输入,Q是输出的上一状态,Q*是输出的下一状态。
D触发器时钟分频
代码
`timescale 1ns/1ns
module even_div
(
input wire rst ,
input wire clk_in,
output wire clk_out2,
output wire clk_out4,
output wire clk_out8
);
//*************code***********//
reg clk_out2_r, clk_out4_r, clk_out8_r;
always@(posedge clk_in or negedge rst) begin
if(~rst)
clk_out2_r <= 0;
else
clk_out2_r <= ~clk_out2_r;
end
always@(posedge clk_out2 or negedge rst) begin
if(~rst)
clk_out4_r <= 0;
else
clk_out4_r <= ~clk_out4_r;
end
always@(posedge clk_out4 or negedge rst) begin
if(~rst)
clk_out8_r <= 0;
else
clk_out8_r <= ~clk_out8_r;
end
assign clk_out2 = clk_out2_r;
assign clk_out4 = clk_out4_r;
assign clk_out8 = clk_out8_r;
//*************code***********//
endmodule