题目：输入序列连续的序列检测

本来是这样写的，可以实现功能，但是有点怪；

timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

    reg[7:0] n_state,c_state;
    
    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
             c_state <= 0;
        else 
             c_state <= n_state;
    reg flag;
    always @ (posedge clk or negedge rst_n)
        if(!rst_n)
        begin
            flag <= 0;
            n_state <= 0;
            end
        else 
            begin
                case(n_state)
                    8'd0:     
                        if (a==0)
                            n_state <= 8'd1;
                        else
                            n_state <= 0;
                    8'd1:     //0
                        if(a==1)
                            n_state <= 8'd2;
                        else
                            n_state <=  8'd1;
                    8'd2:     //01
                        if(a==1)
                            n_state <= 8'd3;
                        else
                            n_state <= 8'd2;
                    
                    8'd3:     //011
                        if(a==1)
                            n_state <= 8'd4;
                        else
                            n_state <= 8'd3;     
                    
                    8'd4:     //0111
                        if(a==0)
                            n_state <= 8'd5;
                        else
                            n_state <=8'd4;
                    8'd5:     //0111 0
                        if(a==0)
                            n_state <= 8'd6;
                        else
                            n_state <= 8'd2;
                    8'd6:     //0111 00
                        if(a==0)
                            n_state <= 8'd7;
                        else
                            n_state <= 8'd2;
                    8'd7:     //0111 000
                        if(a==1)
                        begin
                            flag <= 1;
                            n_state <= 8'd8;
                         end
                        else
                            n_state <= 8'd2;
                     8'd8:     //0111 0001
                     begin
                            n_state <= 8'd0;
                            flag <= 0;
                            end
                    default:  n_state <= 8'd0; 
                endcase 
            end
        always @ (posedge clk or negedge rst_n)
        if (!rst_n)
             match <= 0;
         else if(flag)
              match <= 1;
         else
               match <= 0;  
endmodule

现在做一点修改：

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output wire match
	);

    reg[7:0] n_state,c_state;
   //状态转移 
    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
             c_state <= 0;
        else 
             c_state <= n_state;
 //状态转移条件
    always @ (*)
        if(!rst_n)
        begin
            n_state <= 0;
            end
        else 
            begin
                case(c_state)
                    8'd0:     
                        if (a==0)
                            n_state <= 8'd1;
                        else
                            n_state <= 0;
                    8'd1:     //0
                        if(a==1)
                            n_state <= 8'd2;
                        else
                            n_state <=  8'd1;
                    8'd2:     //01
                        if(a==1)
                            n_state <= 8'd3;
                        else
                            n_state <= 8'd2;
                    
                    8'd3:     //011
                        if(a==1)
                            n_state <= 8'd4;
                        else
                            n_state <= 8'd3;     
                    
                    8'd4:     //0111
                        if(a==0)
                            n_state <= 8'd5;
                        else
                            n_state <=8'd4;
                    8'd5:     //0111 0
                        if(a==0)
                            n_state <= 8'd6;
                        else
                            n_state <= 8'd2;
                    8'd6:     //0111 00
                        if(a==0)
                            n_state <= 8'd7;
                        else
                            n_state <= 8'd2;
                    8'd7:     //0111 000
                        if(a==1)
                        begin
                            n_state <= 8'd8;
                         end
                        else
                            n_state <= 8'd2;
                     8'd8:     //0111 0001
                            begin
                            n_state <= 8'd0;
                            end
                    default:  n_state <= 8'd0; 
                endcase 
            end
    //判断输出
    assign match = (c_state == 8'd7)? a:0;
  
endmodule

结果还是不行，给出的问题是这样： 可以看到在a发生变化之后（第8位要求是1）；在下一个时钟检测到满足序列条件，参考答案在下一个时钟才输出match，并且我的match只有半个周期，上升沿到达就无了； 按照要求应该在检测到后的下一时钟输出match；