`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
    reg [3:0] myRAM [127:0];
    reg [3:0] r_data_r;
    
  	// 写入RAM
    genvar i;
    generate
        for(i=0;i<128;i=i+1)
            always@(posedge clk or negedge rst) begin
                if(~rst)
                    myRAM[i] <= 0;
                else
                    myRAM[addr] <= enb? w_data: myRAM[addr];
            end
                    
    endgenerate
            
  	// 读取RAM
    always@(*) begin
        if(~rst)
            r_data_r <= 0;
        else
            r_data_r <= ~enb? myRAM[addr]: r_data_r;
    end

    assign r_data = r_data_r;
//*************code***********//
endmodule