题解 | #占空比50%的奇数分频#

简析

clk_pos是周期为7且在clk_in上升沿翻转的信号， clk_neg是周期为7且在clk_in下降沿翻转的信号。二者的占空比都是$\frac{3}{7}\backslash frac\{3\}\{7\}$。最后clk_out7等于二者相或。
上面的波形图是用WaveDrom画出来的，它还可以绘制门电路图，也是Github上的开源项目，很推荐。
波形图代码：

{signal: [
  {name: 'clk_in',     wave: 'n............', period:2},
  {name: 'rst',     wave: '0.1.......................'},
  {name: 'cnt',     wave: '=..3.4.5.6.7.8.=.=.=.=.=.=', data:["0","1","2","3","4","5","6","0","1","2","3","4","5","6"]},
  {name: 'clk_pos', wave: '0........1.....0.......1..', phase:0},
  {name: 'clk_neg', wave: '0.......1.....0.......1...', phase:0},
  {name: 'clk_out', wave: '0.......1......0......1...', phase:0},
  {node:'.a......b......c',phase:0}
],
 edge: ['a<->b 3.5', 'b<->c 3.5'],
head:{
   text:'占空比50%的7分频', 
 },}

代码

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
    reg clk_neg, clk_pos;
    reg [2:0] cnt;
    
    always@(posedge clk_in or negedge rst) begin
        if(~rst)
            cnt <= 0;
        else
            cnt <= cnt==6? 0: cnt+1;
    end
    
    always@(posedge clk_in or negedge rst) begin
        if(~rst)
            clk_pos <= 0;
        else
            clk_pos <= cnt==3||cnt==6? ~clk_pos: clk_pos;
    end
    
    always@(negedge clk_in or negedge rst) begin
        if(~rst)
            clk_neg <= 0;
        else
            clk_neg <= cnt==3||cnt==6? ~clk_neg: clk_neg;
    end

    assign clk_out7 = clk_neg|clk_pos;
//*************code***********//
endmodule