题解 | #状态机-非重叠的序列检测#

简析

本状态机的状态转移图如下：

上面六种状态分别代表已接收到0个......5个有效数据。本题和不重叠序列检测不同，后者要求以每六个输入为一组，所以需要配合计数器，而本题不用。

代码

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5;
    reg [2:0] state, nstate;

    always@(posedge clk or posedge rst) begin
        if(~rst)
            state <= S0;
        else
            state <= nstate;
    end
    
    always@(*) begin
        if(~rst)
            nstate <= S0;
        else
            case(state)
                S0     : nstate <= data? S1: S0;
                S1     : nstate <= data? S1: S2;
                S2     : nstate <= data? S3: S0;
                S3     : nstate <= data? S4: S2;
                S4     : nstate <= data? S5: S2;
                S5     : nstate <= data? S1: S0;
                default: nstate <= S0;
            endcase
    end
    
    always@(*) begin
        if(~rst)
            flag <= 0;
        else
            flag <= state==S5;
    end
//*************code***********//
endmodule