题目：数据串转并电路

注意：valid——a信号拉高六个周期后，valid——b输出一个周期的高电平，同时输出此时的数据 先写试试：

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	wire 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    assign  ready_a = 1;
    reg [4:0] cnt;
    reg [5:0] a_reg;
    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin
            a_reg <= 0;
            end
       else if (valid_a)
            a_reg <= { data_a,a_reg[5:0]}; 
            else 
            a_reg <= a_reg; 

      always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin
            cnt <= 0;
            end
       else if (valid_a)
               if(cnt < 5'd6)
                cnt <= cnt + 1; 
               else 
                cnt <= 0;
            else 
              cnt <= cnt; 
   
    always @ (posedge clk or negedge rst_n)
       if (!rst_n)
        valid_b <= 0;
       else if (cnt == 5'd6)
             valid_b <= 1;
            else 
             valid_b <= 0;
             
      always @ (*)
       if (!rst_n)
        data_b <= 0;     
       else if(valid_b)  
            data_b <= a_reg;
            else 
            data_b <= data_b;
             
   
endmodule

仿真后波形：

有两个问题：1：valid_b 应该在valid_a 拉高6个周期后立刻拉起，我慢了一个周期； 2，数据没有进去；

这里我本来是想和前面寄存器一样从后面写入，逐位写入，但是题目要求中写入的是101001 读出的是100101，所以我想当然的认为把进位从后面挪到前面就行，看来是有问题的； 我将数据寄存器改为 a_reg <= { a_reg[5:0] ,data_a}; 仿真图如下，也能看出明显数据错位了；

在查阅了相关资料后，告诉我应该这么写： a_reg <= { data_a , a_reg[5:1]}; 顺便解决计数器的错位：我们将valib_b的输出模块改为所有电平敏感，不再等待时钟；

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	wire 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    assign  ready_a = 1;
    reg [4:0] cnt;
    reg [5:0] a_reg;
    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin
            a_reg <= 0;
            end
       else if (valid_a)
            a_reg <= { data_a ,a_reg[5:1]}; 
            else 
            a_reg <= a_reg; 

      always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin
            cnt <= 0;
            end
       else if (valid_a)
               if(cnt < 5'd6)
                cnt <= cnt + 1; 
               else 
                cnt <= 0;
            else 
              cnt <= cnt; 
   
    always @ (*)
       if (!rst_n)
        valid_b <= 0;
       else if (cnt == 5'd6)
             valid_b <= 1;
            else 
             valid_b <= 0;
             
      always @ (*)
       if (!rst_n)
        data_b <= 0;     
       else if(valid_b)  
            data_b <= a_reg;
            else 
            data_b <= data_b;
             
   
endmodule

仿真脚本：

`timescale 1ns / 1ps
module tb();
 reg clk = 0;
 always #5 clk = !clk;

	

	
	reg 				rst_n	;	
	reg				valid_a	;
	reg	 			data_a		;
 
      wire 		ready_a	;	
      wire			valid_b		;
	  wire [5:0] 	data_b;
	

	
s_to_p s_to_p(
	.clk 		(clk),   
	.rst_n		(rst_n),
	.valid_a	(valid_a)	,
	.data_a		(data_a),
 	.ready_a	(ready_a)	,
 	.valid_b	(valid_b)	,
	. 	data_b  (data_b)
);
	
    initial 
      begin 
       rst_n <= 0; data_a <= 0;  valid_a <= 0;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
       //010110
       
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
       
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 0;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 0;
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
       //101010
       #10 rst_n <= 1;   data_a <= 1;  valid_a <= 1;
       #10 rst_n <= 1;   data_a <= 0;  valid_a <= 1;
      
   
     end

  endmodule

仿真波形;

v_a拉高6个周期后正常，不知道为啥newcode不给过，错误：

根据波形图：在v_b下个周期来之前数据是不变的，但是参考却不是这样，算了，结束；

本次错误： 移位寄存器进位左移：a_reg <= { a_reg[5:0] ,data_a }; 移位寄存器进位右移：a_reg <= { data_a , a_reg[5:1]};