3-8译码器

3-8译码器也是数字电路的基础之一。相关芯片资料可参考链接SNx4HC138 3线路至8线路解码器/多路信号分离器。
引脚图：
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电路图：
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真值表：
alt
关系式：
当片选输入端E3==1且E2_n+E1_n==0时，输入输出有下述关系：

{Y0n=A2‾ A1‾ A0‾‾,Y1n=A2‾ A1‾ A0‾,Y2n=A2‾ A1 A0‾‾,Y3n=A2‾ A1 A0‾,Y4n=A2 A1‾ A0‾‾,Y5n=A2 A1‾ A0‾,Y6n=A2 A1 A0‾‾,Y7n=A2 A1 A0‾,\left\{ \begin{array}{lr} Y_{0n}=\overline{\overline{A_2}\ \overline{A_1}\ \overline{A_0}}, \\ Y_{1n}=\overline{\overline{A_2}\ \overline{A_1}\ A_0}, \\ Y_{2n}=\overline{\overline{A_2}\ A_1\ \overline{A_0}}, \\ Y_{3n}=\overline{\overline{A_2}\ A_1\ A_0}, \\ Y_{4n}=\overline{A_2\ \overline{A_1}\ \overline{A_0}}, \\ Y_{5n}=\overline{A_2\ \overline{A_1}\ A_0}, \\ Y_{6n}=\overline{A_2\ A_1\ \overline{A_0}}, \\ Y_{7n}=\overline{A_2\ A_1\ A_0}, \\ \end{array} \right.

当片选输入端E3==0或者E2_n+E1_n==1时, 输出全部都是1。

代码

一招鲜，和之前的8-3编码器一样使用casez。

`timescale 1ns/1ns
module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
    reg Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r;
    always@(*) begin
        casez({E3, E2_n, E1_n, A2, A1, A0})
            6'b?1?_???: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
            6'b??1_???: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
            6'b0??_???: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
            6'b100_000: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0111_1111;
            6'b100_001: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1011_1111;
            6'b100_010: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1101_1111;
            6'b100_011: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1110_1111;
            6'b100_100: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_0111;
            6'b100_101: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1011;
            6'b100_110: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1101;
            6'b100_111: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1110;
            default:    {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
        endcase
    end
    assign {Y0_n, Y1_n, Y2_n, Y3_n, Y4_n, Y5_n, Y6_n, Y7_n} = {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r};
endmodule