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题解 | #不重叠序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output wire match, output wire not_match ); reg [6:0]reg_data; ...

2024-02-22

0 161

题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [9:0]cur_state; reg [9:0]nex_state; param...

2024-02-22

0 134

题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0]cur_state; reg [8:0]nex_state; para...

2024-02-22

0 148

题解 | #边沿检测#

`timescale 1ns/1ns module edge_detect( input clk, input rst_n, input a, output reg rise, output reg down ); reg a1; always @ (posedge clk or ne...

2024-02-21

0 155

题解 | #ROM的简单实现#

`timescale 1ns/1ns module rom( input clk, input rst_n, input [7:0]addr, output [3:0]data ); reg [3:0] romreg[7:0]; integer i; always @ (posedge ...

2024-02-21

0 163

题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns module seq_circuit( input C , input clk , input rst_n, output wire ...

2024-02-21

0 174

题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns module seq_circuit( input A , input clk , input rst_n, ou...

2024-02-21

0 133

题解 | #使用8线-3线Ⅰ实现16线-4线优先编码器#

`timescale 1ns/1ns module encoder_83( input [7:0] I , input EI , output wire [2:0] Y , output wi...

2024-02-21

0 173

题解 | #优先编码器Ⅰ#

`timescale 1ns/1ns module encoder_83( input [7:0] I , input EI , output wire [2:0] Y , output w...

2024-02-21

0 169

题解 | #用优先编码器①实现键盘编码电路#

`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); always @(*)begin casex(I_n) ...

2024-02-21

0 132