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题解 | #自动贩售机2#

`timescale 1ns/1ns module seller2( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire sel , output reg out1, out...

2024-02-23

0 178

题解 | #自动贩售机1#

`timescale 1ns/1ns module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 , output reg out1, outpu...

2024-02-23

0 142

题解 | #时钟分频（偶数）#

`timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in, output wire clk_out2, output wire clk_out4...

2024-02-23

0 168

题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********...

2024-02-23

0 123

题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns module sequence_test1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********...

2024-02-23

0 145

题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns module width_8to16( input clk , input rst_n , input valid_in , input [7:0] data_in , o...

2024-02-23

0 153

题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg va...

2024-02-22

0 128

题解 | #数据累加输出#

`timescale 1ns/1ns module valid_ready( input clk , input rst_n , input [7:0] data_in , input valid_a , input ready_b , ...

2024-02-22

0 144

题解 | #数据串转并电路#

`timescale 1ns/1ns module s_to_p( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , o...

2024-02-22

0 156

题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); reg [1:0]cs,ns; always@(...

2024-02-22

0 137