神气的小笼包

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题解 | #流水线乘法器#

`timescale 1ns/1ns module multi_pipe#( parameter size = 4 )( input clk , input rst_n , input [size-1:0] mul_a , input [size...

2023-08-01

0 218

题解 | #Johnson Counter#

`timescale 1ns/1ns module JC_counter( input clk , input rst_n, output reg [3:0] Q ); always@(posedge ...

2023-07-28

2 241

题解 | #单端口RAM#

`timescale 1ns/1ns module RAM_1port( input clk, input rst, input enb, input [6:0]addr, input [3:0]w_data, output wire [3:0]r_...

2023-07-28

0 242

题解 | #简易秒表#

`timescale 1ns/1ns module count_module( input clk, input rst_n, output reg [5:0]second, output reg [5:0]minute ); reg stop_flag; alw...

2023-07-28

0 300

题解 | #可置位计数器#

`timescale 1ns/1ns module count_module( input clk, input rst_n, input set, input [3:0] set_num, output reg [3:0]number, output reg zero ); re...

2023-07-28

0 241

题解 | #RAM的简单实现#

`timescale 1ns/1ns module ram_mod( input clk, input rst_n, input write_en, input [7:0]write_addr, input [3:0]write_data, input read_en, inp...

2023-07-28

0 287

题解 | #状态机与时钟分频#

`timescale 1ns/1ns module huawei7( input wire clk , input wire rst , output reg clk_out ); parameter s0 = 4'b0001, s1 = 4'b0010, s2 = 4'...

2023-07-28

0 270

题解 | #并串转换#

`timescale 1ns/1ns module huawei5( input wire clk , input wire rst , input wire [3:0]d , output wire valid_in , output wire dout ); //*******...

2023-07-28

0 241