神气的小笼包

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题解 | #超前进位加法器#

`timescale 1ns/1ns module huawei8//四位超前进位加法器 ( input wire [3:0]A, input wire [3:0]B, output wire [4:0]OUT ); //*************code***********//...

2023-08-08

0 257

题解 | #全加器#

`timescale 1ns/1ns module add_half( input A , input B , output wire S , output wire ...

2023-08-04

0 255

题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns module det_moore( input clk , input rst_n , input din , output reg ...

2023-08-04

0 324

题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); reg [2:0] data_reg; alwa...

2023-08-03

0 215

题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0] data; reg [3:0] bit_cnt; reg flag; ...

2023-08-03

0 234

题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [7:0] data; reg [2:0] bit_cnt; reg flag; ...

2023-08-03

0 206

题解 | #数据累加输出#

`timescale 1ns/1ns module valid_ready( input clk , input rst_n , input [7:0] data_in , input valid_a , input ready_b , ...

2023-08-03

0 237

题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg va...

2023-08-03

0 257

题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns module width_8to12( input clk , input rst_n , input valid_in , input [7:0] data_in , o...

2023-08-03

0 320

题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns module width_8to16 ( input clk , input rst_n , input valid_in, input [7:0] data_in , output reg vali...

2023-08-03

0 275