神气的小笼包

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题解 | #数据串转并电路#

`timescale 1ns/1ns module s_to_p ( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , ...

2023-08-03

0 234

题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********...

2023-08-02

0 269

题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns module sequence_test1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********...

2023-08-02

0 255

题解 | #时钟分频（偶数）#

`timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in, output wire clk_out2, output wire clk_out4...

2023-08-02

0 274

题解 | #任意小数分频#

`timescale 1ns/1ns module div_M_N( input wire clk_in, input wire rst, output wire clk_out ); parameter M_N = 8'd87; parameter c89 = 8'd24; // 8...

2023-08-02

0 303

题解 | #自动贩售机2#

`timescale 1ns/1ns module seller2( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire sel , output reg out1, out...

2023-08-02

0 264

题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns module odo_div_or ( input wire rst , input wire clk_in, output wire clk_out7 ); //*************code...

2023-08-02

1 265

题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns module fsm2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// parame...

2023-08-02

0 266

题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns module fsm1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// paramet...

2023-08-02

0 348

题解 | #游戏机计费程序#

`timescale 1ns/1ns module game_count ( input rst_n, //异位复位信号，低电平有效 input clk, //时钟信号 input [9:0]money, input set...

2023-08-02

0 296