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题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns module seq_circuit( input ...

2022-09-16

0 234

题解 | #数据选择器实现逻辑电路#

`timescale 1ns/1ns module data_sel( input S0...

2022-09-16

0 217

题解 | #使用3-8译码器①实现逻辑函数#

`timescale 1ns/1ns module decoder_38( input ...

2022-09-16

0 237

题解 | #用3-8译码器实现全减器#

`timescale 1ns/1ns module decoder_38( input ...

2022-09-14

0 261

题解 | #8线-3线优先编码器实现16线-4线优先编码器#

`timescale 1ns/1ns module encoder_83( input [7:0] &n...

2022-09-14

0 406

题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns module lca_4( input [3:0] A_in&nb...

2022-09-14

0 255

题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns module lca_4( input [3:0] A_in&nb...

2022-09-14

0 242

题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); &n...

2022-08-08

0 282

题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); &n...

2022-08-08

0 212

题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns module sequence_test1( input wire clk , input wire rst , input wire&nb...

2022-08-08

1 333