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全部文章（共51篇）

题解 | #任意小数分频#

`timescale 1ns/1ns module div_M_N( input wire clk_in, input wire rst, output reg clk_out ); parameter M_N = 8'd87; parameter c89 = 8'd24; // 8/...

2023-05-25

0 322

题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); reg data_valid_d; alway...

2023-05-24

0 257

题解 | #不重叠序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); reg[3:0]cnt; reg [...

2023-05-24

0 284

题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0]buff; always@(posedge clk or negedge r...

2023-05-24

0 188

题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg[7:0]buff; always@(posedge clk or negedge r...

2023-05-24

0 278

题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns module fsm2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// parame...

2023-05-24

0 276

题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns module fsm1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// paramet...

2023-05-24

0 323

题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns module odd_div ( input wire rst , input wire clk_in, output reg clk_out5 ); //*************code********...

2023-05-24

0 249

题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns module odo_div_or ( input wire rst , input wire clk_in, output wire clk_out7 ); //*************code...

2023-05-24

0 259

题解 | #时钟分频（偶数）#

`timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in, output reg clk_out2, output reg clk_out4, ...

2023-05-24

2 415