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全部文章（共51篇）

题解 | #自动贩售机1#

`timescale 1ns/1ns module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 , output reg out1, outpu...

2023-05-31

1 397

题解 | #十六进制计数器#

`timescale 1ns/1ns module counter_16( input clk , input rst_n , output reg [3:0] Q ); always@(po...

2023-05-31

1 390

题解 | #全加器#

`timescale 1ns/1ns module add_half( input A , input B , output wire S , output wire ...

2023-05-31

0 294

题解 | #串行进位加法器#

`timescale 1ns/1ns module add_4( input [3:0] A , input [3:0] B , input Ci , output wire [3:0] S ...

2023-05-31

0 346

题解 | #单端口RAM#

`timescale 1ns/1ns module RAM_1port( input clk, input rst, input enb, input [6:0]addr, input [3:0]w_data, output wire [3:0]r_...

2023-05-30

0 306

题解 | #数据串转并电路#

`timescale 1ns/1ns module s_to_p( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , o...

2023-05-30

0 248

题解 | #状态机与时钟分频#

`timescale 1ns/1ns module huawei7( input wire clk , input wire rst , output reg clk_out ); //*************code***********// parameter s0=0; par...

2023-05-30

0 293

题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg data_in_reg; always@(posedge clk or negedge r...

2023-05-30

0 365

题解 | #任意奇数倍时钟分频#

`timescale 1ns/1ns module clk_divider #(parameter dividor = 5) ( input clk_in, input rst_n, output clk_out ); reg [$clog2(dividor):0] cnt1...

2023-05-30

0 332

题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns module det_moore( input clk , input rst_n , input din , output reg ...

2023-05-30

0 284