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题解 | #同步FIFO#

`timescale 1ns/1ns /**********************************RAM************************************/ module dual_port_RAM #(parameter DEPTH = 16, p...

2023-05-30

0 218

题解 | #时钟切换#

`timescale 1ns/1ns module huawei6( input wire clk0 , input wire clk1 , input wire rst , input wire sel , output wire clk_out ); //***********...

2023-05-30

0 263

题解 | #异步复位同步释放#

`timescale 1ns/1ns module ali16( input clk, input rst_n, input d, output reg dout ); //*************code***********// reg a1; reg a2; wire rst_o; a...

2023-05-30

0 254

题解 | #数据累加输出#

`timescale 1ns/1ns module valid_ready( input clk , input rst_n , input [7:0] data_in , input valid_a , input ready_b , ...

2023-05-30

0 218

题解 | #异步FIFO#

`timescale 1ns/1ns /***************************************RAM*****************************************/ module dual_port_RAM #(parameter DEPTH = 16,...

2023-05-28

1 258

题解 | #格雷码计数器#

`timescale 1ns/1ns module gray_counter( input clk, input rst_n, output reg[3:0] gray_out ); //格雷码转二进制 wire [3:0]bin_wire; assign bin_w...

2023-05-26

0 306

题解 | #ROM的简单实现#

`timescale 1ns/1ns module rom( input clk, input rst_n, input [7:0]addr, output [3:0]data ); reg [3:0]data; reg [3:0]buff[7:0]; always@(posedge ...

2023-05-26

0 235

题解 | #同步FIFO#

`timescale 1ns/1ns /**********************************RAM************************************/ module dual_port_RAM #(parameter DEPTH = 16, pa...

2023-05-26

1 242

题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********...

2023-05-25

0 287

题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns module sequence_test1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********...

2023-05-25

0 236