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题解 | #加减计数器#

`timescale 1ns/1ns module count_module( input clk, input rst_n, input mode, output reg [3:0]number, output reg zero ); reg [3:0]num; always@(po...

2023-05-23

0 217

题解 | #简易秒表#

`timescale 1ns/1ns module count_module( input clk, input rst_n, output reg [5:0]second, output reg [5:0]minute ); always@(posedge clk ...

2023-05-23

0 186

题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg va...

2023-05-23

0 231

题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns module width_8to12( input clk , input rst_n , input valid_in , input [7:0] data_in , o...

2023-05-22

0 250

题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns module width_8to16( input clk , input rst_n , input valid_in , input [7:0] data_in , o...

2023-05-22

0 212

题解 | #奇偶校验#

`timescale 1ns/1ns module odd_sel( input [31:0] bus, input sel, output check ); //*************code***********// wire odd; wire even; wire check; assi...

2023-04-21

0 221

题解 | #数据选择器实现逻辑电路#

`timescale 1ns/1ns module data_sel( input S0 , input S1 , input D0 , input D1...

2023-04-21

1 275

题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns module seq_circuit( input C , input clk , input rst_n, output wire ...

2023-04-21

0 203

题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns module seq_circuit( input A , input clk , input rst_n, ou...

2023-04-21

0 422

题解 | #实现3-8译码器①#

`timescale 1ns/1ns module decoder_38( input E1_n , input E2_n , input E3 , input ...

2023-03-29

1 272