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题解 | #编写乘法器求解算法表达式#

`timescale 1ns/1ns module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); reg[8:0]c; wire [8:0]out1,out2...

2023-06-08

0 431

题解 | #乘法与位运算#

`timescale 1ns/1ns module dajiang13( input [7:0] A, output [15:0] B ); //*************code***********// wire [15:0]buff [0:7]; assign...

2023-06-08

0 409

题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps module pulse_detect( input clka , input clkb , input rst_n , input sig_a , output sig_b ); //典...

2023-06-08

1 735

题解 | #并串转换#

`timescale 1ns/1ns module huawei5( input wire clk , input wire rst , input wire [3:0]d , output wire valid_in , output wire dout ); //*******...

2023-06-08

1 326

题解 | #游戏机计费程序#

`timescale 1ns/1ns module game_count ( input rst_n, //异位复位信号，低电平有效 input clk, //时钟信号 input [9:0]money, input set, in...

2023-06-05

0 487

题解 | #Johnson Counter#

`timescale 1ns/1ns module JC_counter( input clk , input rst_n, output reg [3:0] Q ); reg [2:0]cnt; alw...

2023-06-01

0 318

题解 | #多bit MUX同步器#

`timescale 1ns/1ns module mux( input clk_a , input clk_b , input arstn , input brstn , input [3:0] data_in , input ...

2023-06-01

0 415

题解 | #RAM的简单实现#

`timescale 1ns/1ns module ram_mod( input clk, input rst_n, input write_en, input [7:0]write_addr, input [3:0]write_data, input read_en, inp...

2023-06-01

0 375

题解 | #序列发生器#

`timescale 1ns/1ns module sequence_generator( input clk, input rst_n, output reg data ); reg [2:0]cnt; always@(posedge clk or negedge rst_n)begi...

2023-06-01

1 354

题解 | #自动贩售机2#

`timescale 1ns/1ns module seller2( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire sel , output reg out1, out...

2023-05-31

0 476