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Verilog 进阶挑战

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题解 | #信号级联合并#

`timescale 1ns/1ns module top_module( input [4:0] a, b, c, d, e, f, output [7:0] w, x, y, z ); wire [31:0] data ; assign data = {a,...

2023-05-23

5 338

题解 | #对信号按位操作#

`timescale 1ns/1ns module top_module( input [4:0] in, output out_and, output out_or, output out_xor ); assign out_and = &in[4:0...

2023-05-23

14 412

题解 | #对信号按位操作#

`timescale 1ns/1ns module top_module( input [4:0] in, output out_and, output out_or, output out_xor ); assign out_and = &in[4:0...

2023-05-23

3 276

题解 | #信号顺序调整#

`timescale 1ns/1ns module top_module( input wire [12:0] in , output wire [12:0] out ); wire [3:0] a,b,c,d; assign {a,b,c,d...

2023-05-23

26 741