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题解 | #非整数倍数据位宽转换8to12#

module width_8to12( input clk , input rst_n , input valid_in , input [7:0] data_in , output reg vali...

2023-05-21

0 220

题解 | #整数倍数据位宽转换8to16#

module width_8to16( input clk , input rst_n , input valid_in , input [7:0] data_in , output reg valid_ou...

2023-05-20

0 317

题解 | #可置位计数器#

`timescale 1ns/1ns module count_module( input clk, input rst_n, input set, input [3:0] set_num, output reg [3:0]number, output reg zero ); ...

2023-05-20

0 213

题解 | #加减计数器#

module count_module( input clk, input rst_n, input mode, output reg [3:0]number, output reg zero ); reg [3:0]out; always @ (posedge clk or nege...

2023-05-20

0 243

题解 | #简易秒表#

module count_module( input clk, input rst_n, output reg [5:0]second, output reg [5:0]minute ); always @ (posedge clk or negedge rst_n ) be...

2023-05-20

0 220

题解 | #状态机-重叠序列检测#

module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;...

2023-05-20

0 217

题解 | #状态机-非重叠的序列检测#

module sequence_test1( input wire clk , input wire rst , input wire data , output reg flag ); parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,...

2023-05-20

2 276

题解 | #任意小数分频#

`timescale 1ns/1ns module div_M_N( input wire clk_in, input wire rst, output wire clk_out ); parameter M_N = 8'd87; parameter c89 = 8'd24; // 8...

2023-05-20

0 0

题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns module odo_div_or ( input wire rst , input wire clk_in, output wire clk_out7 ); //*************code...

2023-05-19

0 247

题解 | #时钟分频（偶数）#

`timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in, output wire clk_out2, output wire clk_out4...

2023-05-17

0 227