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题解 | #流水线乘法器#

`timescale 1ns/1ns module multi_pipe#( parameter size = 4 )( input clk , input rst_n , input [size-1:0] mul_a , input [size...

2023-05-30

0 221

题解 | #Johnson Counter#

`timescale 1ns/1ns module JC_counter( input clk , input rst_n, output reg [3:0] Q ); always @(posedge ...

2023-05-30

0 176

题解 | #自动贩售机2#

module seller2( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire sel , output reg out1, output reg out2, outpu...

2023-05-30

0 187

题解 | #格雷码计数器#

module gray_counter( input clk, input rst_n, output reg [3:0] gray_out ); reg[3:0] count; reg clk_2; always @(posedge clk or negedge rst...

2023-05-30

0 176

题解 | #自动贩售机1#

module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 , output reg out1, output reg [1:0]out2 ); ...

2023-05-22

0 320

题解 | #RAM的简单实现#

`timescale 1ns/1ns module ram_mod( input clk, input rst_n, input write_en, input [7:0]write_addr, input [3:0]write_data, input read_en, inp...

2023-05-22

0 219

题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns module det_moore( input clk , input rst_n , input din , output reg ...

2023-05-21

0 300

题解 | #序列发生器#

module sequence_generator( input clk, input rst_n, output reg data ); reg [2:0] cnt; always @(posedge clk or negedge rst_n) begin if(!rst_n) begin...

2023-05-21

0 236

题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg data,temp; always @(posedge clk or negedge rst...

2023-05-21

0 225

题解 | #非整数倍数据位宽转换24to128#

module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg valid_out , output r...

2023-05-21

1 398