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题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns module odd_div ( input wire rst , input wire clk_in, output wire clk_out5 ); //*************code*******...

2023-05-17

0 181

题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns module fsm1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// paramet...

2023-05-14

0 216

题解 | #数据串转并电路#

`timescale 1ns/1ns module s_to_p( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , o...

2023-05-14

0 201

题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); parameter s0=3'd0,s1=3'd1,s...

2023-05-14

1 282

题解 | #不重叠序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); parameter s0=4'd0; pa...

2023-05-14

0 251

题解 | #逻辑运算2#

`timescale 1ns/1ns module top_module ( input a, input b, input c, input d, output e, output f ); wire temp0,temp1,temp2; assign temp0=a&b, te...

2023-05-10

0 188

题解 | #模拟逻辑芯片#

`timescale 1ns/1ns module top_module ( input p1a, p1b, p1c, p1d, p1e, p1f, output p1y, input p2a, p2b, p2c, p2d, output p2y ); wir...

2023-05-10

2 263

题解 | #逻辑运算#

`timescale 1ns/1ns module top_module ( input a, input b, input c, input d, output e, output f ); wire r_and,r_or; assign r_and=a&b; assign r_or...

2023-05-10

2 224

题解 | #XOR 门#

`timescale 1ns/1ns module top_module( input a, input b, output c ); assign c=a^b; endmodule

2023-05-10

0 212

题解 | #NOR 门#

`timescale 1ns/1ns module top_module( input a, input b, output c, output d); assign d=a|b; assign c=~d; endmodule

2023-05-10

0 245